A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

In this paper, a high-speed low-power SAR ADC is designed. prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture proposed, showing more power efficiency and suitable for data converters. Meanwhile, synchronous timing strategy employed, achieving flexible time allocation of DAC settling comparison in each bit-cycle. addition, two-stage non-tail-current-source single-phase-clock comparator proposed power-efficiency compatible resolving time. The prototype fabricated 40nm CMOS technology occupies active area 0.04mm2. An SNDR 57.18dB SFDR 75.29dB are achieved Nyquist rate input at sampling 160MS/s, consuming 1.3mW 1.1V supply voltage.